This invention relates generally to a process for fabricating CMOS devices, and more specifically to an improved process for providing isolation between CMOS devices.
Many integrated circuit devices are being designed today using CMOS technology. The trend of these integrated circuits is towards larger circuit functions, more complex device structures, and a reduction in device size. The complexity and size of the devices makes it difficult to design manufacturing processes that are both high yielding and reliable. It is necessary, therefore, that any process be designed to reduce manufacturing steps and to make each manufacturing step highly reproducible.
Electrical isolation between individual devices of the integrated circuit is accomplished by a thick field oxide which is formed between active device regions. The thick field oxide increases the threshold voltage of any parasitic device which may exist between adjacent active regions and prevents the inadvertent electrical coupling of such regions. To insure the electrical isolation, additional doping is used beneath the field oxide, especially in P-type surface regions, to further increase the parasitic threshold voltage. Although the high field threshold voltage is absolutely necessary to the reliable functioning of the integrated circuit device, a properly aligned thick field oxide and (where appropriate) field doping must be accomplished with a minimum of critical processing steps.
Accordingly, a need existed for a process to provide acceptable field isolation between CMOS devices with minimal mask count. In this context, "mask count" refers to the number of photolithographic masking operations that must be performed to fabricate the device.
It is therefore an object of this invention to provide an improved process for fabricating CMOS devices.
It is a further object of this invention to provide an improved process for fabricating CMOS devices with acceptable levels of electrical isolation between adjacent devices.
It is a still further object of this invention to provide an improved process for fabricating CMOS devices with a minimum of masking operations.